Q(1) When we want to transfer data from the keyboard to the attached computer, which mode of transfer is mostly preferred?
- Options:
(a) Programmed I/O
(b) Direct memory access
(c) Hardware interrupt-driven I/O
(d) Software interrupt-driven I/O - Correct Option: (c) Hardware interrupt-driven I/O
- Explanation: Hardware interrupt-driven I/O is typically used when input is from devices like a keyboard. When a key is pressed, the keyboard sends an interrupt to the CPU, prompting it to transfer data.
Q(2) When we want to transfer data from the hard disk to the attached computer on a page fault, which mode of transfer is mostly preferred?
- Options:
(a) Hardware interrupt-driven I/O
(b) Software interrupt-driven I/O
(c) Direct memory access
(d) Programmed I/O - Correct Option: (c) Direct memory access
- Explanation: Direct memory access (DMA) is used to transfer large blocks of data directly between the memory and peripherals (such as a hard disk) without involving the CPU, making it ideal for handling page faults efficiently.
Q(3) What does the Data Link Escape (DLE) character indicate to the receiving device in a character-oriented data transfer protocol?
- Options:
(a) Start of transfer
(b) End of transfer
(c) A control character
(d) A non-control character - Correct Option: (c) A control character
- Explanation: The Data Link Escape (DLE) character is used to signify that the following character is a control character, often used in data communication protocols to escape special meanings.
Q(4) A typical I/O bus used with a computer is:
- Options:
(a) Synchronous and proprietary
(b) Asynchronous and standard
(c) Synchronous and proprietary
(d) Synchronous and standard - Correct Option: (b) Asynchronous and standard
- Explanation: Most I/O buses are asynchronous, allowing for independent data transfer speeds between the CPU and I/O devices. Standard buses are commonly used for compatibility.
Q(5) In which of the following, the interrupting device provides the address of the interrupt service routine (ISR)?
- Options:
(a) Hardware Interrupt
(b) Software interrupt
(c) Vectored interrupt
(d) Daisy chaining - Correct Option: (c) Vectored interrupt
- Explanation: In vectored interrupts, the interrupting device sends the address of the ISR to the CPU, which allows for faster and more efficient interrupt handling.
Q(6) CPU clock speed refers to the number of:
- Options:
(a) CPUs it has
(b) RAMs it has
(c) Clocks it has
(d) Number of cycles the CPU executes per second - Correct Option: (d) Number of cycles the CPU executes per second
- Explanation: The clock speed refers to the number of clock cycles the CPU can execute per second, often measured in GHz.
Q(7) Which of the following memory has the highest access speed?
- Options:
(a) Hard disk
(b) RAM
(c) ROM
(d) Cache memory - Correct Option: (d) Cache memory
- Explanation: Cache memory is the fastest form of memory in a computer system, located close to the CPU to provide high-speed access to frequently used data.
Q(8) For a 2K x 16 memory system that uses a decoder to select a word, the total number of external connections to the memory system (including address, data, control, and power signals) will be at least:
- Options:
(a) 24
(b) 31
(c) 28
(d) 30 - Correct Option: (a) 24
- Explanation: To calculate the number of external connections, you need to consider address lines, data lines, control signals, and power. For a 2K x 16 system, it requires 11 address lines (since 2K = 2048), 16 data lines, and control and power signals.
Q(9) A memory system of size 16 K bytes is to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is:
- Options:
(a) 2
(b) 4
(c) 6
(d) 8 - Correct Option: (c) 6
- Explanation: To design the memory system, we calculate the total address and data lines needed. A 16K byte system requires 14 address lines (log2(16K) = 14), and each chip provides 12 address lines and 4 data lines. Hence, 6 chips are needed.
Q(10) Which memory improves the speed of execution of a program?
- Options:
(a) Primary
(b) Cache
(c) Secondary
(d) Virtual - Correct Option: (b) Cache
- Explanation: Cache memory improves the speed of program execution by storing frequently accessed data close to the CPU for faster access.
Q(11) In which of the following addressing modes is the operand value directly specified?
- Options:
(a) Indirect
(b) Direct
(c) Immediate
(d) Register direct - Correct Option: (c) Immediate
- Explanation: In immediate addressing mode, the operand is directly specified in the instruction itself, rather than being stored in a memory location.
Q(12) When an instruction is required to be brought from memory to CPU, which one of the following buses is fetched?
- Options:
(a) Data Bus
(b) Address Bus
(c) Control Bus
(d) Peripheral Bus - Correct Option: (a) Data Bus
- Explanation: The data bus is used to transfer the actual instruction (or data) from memory to the CPU.
Q(13) Identify which one of the following is not a data transfer instruction:
- Options:
(a) Load
(b) Clear
(c) Move
(d) Store - Correct Option: (b) Clear
- Explanation: "Clear" is typically used to reset or set a value to zero, whereas Load, Move, and Store are directly related to data transfer operations.
Q(14) The control unit of the computer system is designed to go through which of the following instruction cycles?
- Options:
(a) Fetch
(b) Decode
(c) Execute
(d) All of the above - Correct Option: (d) All of the above
- Explanation: The control unit goes through the fetch, decode, and execute cycles as part of the instruction cycle for every instruction.
Q(15) The function of the program counter (PC) is to hold:
- Options:
(a) Temporary
(b) Address of the next instruction
(c) Memory operand
(d) Address of memory - Correct Option: (b) Address of the next instruction
- Explanation: The Program Counter (PC) holds the address of the next instruction to be executed by the CPU.
Q(16) Identify the incorrect statement with respect to cache memory:
- Options:
(a) The temporal locality takes into account the number of times of execution
(b) The spatial locality takes into account the loading of neighboring variables of an instruction
(c) The contents loaded into cache cannot be overwritten exclusively
(d) The cache memory uses a shorter address space as compared to main memory - Correct Option: (c) The contents loaded into cache cannot be overwritten exclusively
- Explanation: This statement is incorrect because cache contents can be overwritten (evicted) as newer data is loaded. In practice, cache lines are replaced based on certain policies (like LRU).
Q(17) The drawback of building a large memory with DRAM is:
- Options:
(a) The large cost factor
(b) The inefficient memory organization
(c) Slow speed of operation
(d) All of the mentioned - Correct Option: (d) All of the mentioned
- Explanation: DRAM is slower than SRAM and has cost and efficiency issues when scaled to large sizes, which makes it less ideal for certain use cases.
Q(18) The fastest data access is provided using:
- Options:
(a) Cache
(b) DRAM
(c) SRAM
(d) Registers - Correct Option: (d) Registers
- Explanation: Registers, which are small, fast storage locations within the CPU, provide the fastest data access. Cache is fast but slower than registers.
Q(19) The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called:
- Options:
(a) Level 1 cache
(b) Level 2 cache
(c) Register
(d) TLB - Correct Option: (a) Level 1 cache
- Explanation: Level 1 (L1) cache is located inside the CPU and stores copies of frequently accessed data and instructions to speed up access to the main memory.
Q(20) The program is divided into operable parts called as:
- Options:
(a) Frames
(b) Segments
(c) Pages
(d) Sheets - Correct Option: (b) Segments
- Explanation: In memory management, a program can be divided into segments, which are logical divisions of a program, like functions, data, etc.
Q(21) All operations using one-address instructions are done between:
- Options:
(a) Memory and processor registers
(b) Accumulator and processor registers
(c) Accumulator and memory operand
(d) Stack pointer and memory operand - Correct Option: (c) Accumulator and memory operand
- Explanation: In one-address instructions, the operations are typically performed between an accumulator and a memory operand, with the accumulator acting as a temporary storage for results.
Q(22) Which of the following stores operand during execution and result of operation after execution?
- Options:
(a) General purpose registers
(b) Accumulator
(c) Flag register
(d) Stack register - Correct Option: (a) General purpose registers
- Explanation: General-purpose registers store both operands during execution and the result after execution.
Q(23) Addressing mode in which the address field of instruction specifies a register in the CPU, whose contents give the address of the operand in memory is called:
- Options:
(a) Indirect addressing mode
(b) Relative addressing mode
(c) Register indirect addressing mode
(d) Register addressing mode - Correct Option: (c) Register indirect addressing mode
- Explanation: In register indirect addressing mode, the address field contains the register number, and the register’s contents are the memory address of the operand.
Q(24) Address of stored data is not defined in the given instruction, in:
- Options:
(a) Direct addressing mode
(b) Indirect addressing mode
(c) Register addressing mode
(d) Implicit addressing mode - Correct Option: (d) Implicit addressing mode
- Explanation: In implicit addressing mode, no address field is provided because the operand is implicitly defined (e.g., the accumulator).
Q(25) Which of the following is used to store the address of memory from which data is collected and sent to the CPU?
- Options:
(a) Program counter
(b) Memory Address Register
(c) Cache memory
(d) DMA - Correct Option: (b) Memory Address Register
- Explanation: The Memory Address Register (MAR) stores the address of the memory location from which data is to be read or written.
Q(26) What does "coupling of processors" refer to?
- Options:
(a) The synchronization of CPU clock speeds
(b) The interconnection of multiple processors to work together
(c) The integration of memory and CPU in a single chip
(d) The physical connection of processors to the motherboard - Correct Option: (b) The interconnection of multiple processors to work together
- Explanation: Coupling of processors refers to the way multiple processors are interconnected to function together, often seen in multi-core or multi-processor systems.
Q(27) What does the term "memory contention" refer to?
- Options:
(a) Bus contention
(b) Processor affinity
(c) Memory contention
(d) Cache coherence - Correct Option: (c) Memory contention
- Explanation: Memory contention occurs when multiple processors or tasks try to access and modify the same memory location, leading to delays and potential data inconsistency.
Q(28) What is the key advantage of Booth’s Algorithm for binary multiplication compared to traditional methods?
- Options:
(a) Faster addition
(b) Reduced number of operations
(c) Improved division
(d) Enhanced exponentiation - Correct Option: (b) Reduced number of operations
- Explanation: Booth’s Algorithm reduces the number of operations needed for multiplication, particularly when dealing with negative numbers in binary.
Q(29) In binary division, what operation is performed repeatedly to calculate the quotient?
- Options:
(a) Bitwise OR
(b) Bitwise AND
(c) Subtraction
(d) Addition - Correct Option: (c) Subtraction
- Explanation: In binary division, subtraction is performed repeatedly to calculate the quotient by subtracting the divisor from the dividend and determining how many times the divisor fits into the dividend.
Q(30) Which of the following statements is false?
- Options:
(a) The main objective for using cache memory is to increase the effective speed of the memory system.
(b) The main objective for using virtual memory is to increase the effective capacity of the memory system.
(c) The size of main memory is larger as compared to cache memory. Main capacity of the memory system.
(d) Main memory is faster as compared to cache memory. - Correct Option: (d) Main memory is faster as compared to cache memory
- Explanation: This statement is false because cache memory is much faster than main memory (RAM), which is why cache is used to store frequently accessed data to improve speed.
Q(31) The techniques which move the program blocks to or from the physical memory is called as:
- Options:
(a) Paging
(b) Virtual memory organization
(c) Overlays
(d) Framing - Correct Option: (a) Paging
- Explanation: Paging is the technique where data is moved between the program and physical memory in blocks called pages. This allows efficient memory management.
Q(32) The binary address issued to data or instructions are called as:
- Options:
(a) Physical address
(b) Location address
(c) Relocatable address
(d) Logical address - Correct Option: (d) Logical address
- Explanation: The logical address is the address generated by the CPU during a program’s execution, also known as the virtual address.
Q(33) Which is used to implement virtual memory organization?
- Options:
(a) Page table
(b) Frame table
(c) MMU
(d) None - Correct Option: (a) Page table
- Explanation: The page table is used to map logical addresses to physical addresses in virtual memory systems, allowing the operating system to implement virtual memory.
Q(34) The main aim of virtual memory organization is:
- Options:
(a) To provide effective memory access
(b) To provide better memory transfer
(c) To improve the execution of the program
(d) All of the above - Correct Option: (d) All of the above
- Explanation: Virtual memory helps in all of the mentioned ways by providing effective memory access, efficient memory transfer, and improving program execution by making the system appear to have more memory than physically available.
Q(35) How is set-associative mapping different from direct mapping?
- Options:
(a) It uses a single tag to store the corresponding data on index
(b) Direct mapping uses argument registers to match the addresses
(c) It uses two tags against a single index
(d) Direct mapping is very expensive - Correct Option: (c) It uses two tags against a single index
- Explanation: Set-associative mapping uses multiple ways (often 2 or 4) in each set to store data, with two tags to match the data. Direct mapping uses one tag and one index per data location.
Q(36) Memory-mapped I/O has:
- Options:
(a) Increased addressing memory due to the memory-mapped I/O
(b) Decreased addressing memory due to the memory-mapped I/O
(c) Separate control line
(d) None of the above - Correct Option: (a) Increased addressing memory due to the memory-mapped I/O
- Explanation: Memory-mapped I/O uses part of the address space to address memory-mapped devices, thereby increasing the addressing memory space required.
Q(37) Which multiplication algorithm is known for its optimization of runs of 0s and 1s in the multiplier?
- Options:
(a) Non-Restoring Division
(b) Long Division
(c) Booth's Algorithm
(d) Shift-and-Add - Correct Option: (c) Booth's Algorithm
- Explanation: Booth's Algorithm is specifically optimized for situations where there are long runs of 0s or 1s in the multiplier, reducing the number of operations.
Q(38) Which arithmetic operation is typically used to implement subtraction in a computer's hardware?
- Options:
(a) Binary division
(b) Two's complement subtraction
(c) Binary addition
(d) Binary multiplication - Correct Option: (b) Two's complement subtraction
- Explanation: Subtraction is typically implemented using two's complement representation, where subtraction is performed by adding the two's complement of the number to be subtracted.
Q(39) What is the result of adding the binary numbers 1101 and 1011?
- Options:
(a) 1110
(b) 10010
(c) 10100
(d) 11000 - Correct Option: (b) 10010
- Explanation: Adding 1101 and 1011 in binary gives 10010.
Q(40) Which of the micro-operations is correctly labeled (Move the content of R2 register to R1 register)?
- Options:
(a) R1->R2
(b) R1 < R2
(c) R1 = R2
(d) R1 -> R2 - Correct Option: (d) R1 -> R2
- Explanation: The correct notation for moving the contents of R2 to R1 is
R1 <- R2.
Q(41) In a tightly coupled system, how do the processors typically share memory and resources?
- Options:
(a) They have their separate memory and resources.
(b) They communicate via network protocols.
(c) They use a shared global memory.
(d) They do not share memory. - Correct Option: (c) They use a shared global memory.
- Explanation: In a tightly coupled system, multiple processors share a common memory and resources, allowing for efficient data sharing and coordination.
Q(42) Which type of coupling is commonly used in distributed computing environments and clusters?
- Options:
(a) Tightly coupled
(b) Cache Coherent Multiprocessing (CC-NUMA)
(c) Loosely coupled
(d) Symmetric Multiprocessing (SMP) - Correct Option: (c) Loosely coupled
- Explanation: Loosely coupled systems are common in distributed computing, where each processor has its own memory but they communicate over a network.
Q(43) How is memory typically organized in a NUMA (Non-Uniform Memory Access) system?
- Options:
(a) All memory is equally accessible to all processors.
(b) Memory is organized in a single large pool for all processors.
(c) Each processor has its own dedicated memory module.
(d) Memory is divided into different regions, and access times vary. - Correct Option: (d) Memory is divided into different regions, and access times vary.
- Explanation: In NUMA, processors have access to local memory (which they access faster) and remote memory (which they access slower), and access times depend on memory location.
Q(44) How is cache coherence achieved in a cache-coherent multiprocessor system (CC-NUMA)?
- Options:
(a) By increasing CPU clock speed
(b) Through shared memory and coherence protocols - (c) Through distributed memory architecture
(d) By using multiple levels of CPU cache - Correct Option: (b) Through shared memory and coherence protocols
- Explanation: Cache coherence in CC-NUMA systems is maintained using protocols like MESI (Modified, Exclusive, Shared, Invalid), which ensure all processors see a consistent view of memory.
Q(45) The term describes a multiprocessor system where all processors share a common memory:
- Options:
(a) Cache Coherent Multiprocessing (CC-NUMA)
(b) Asymmetric Multiprocessing (AMP)
(c) Distributed Multiprocessing (DMP)
(d) Symmetric Multiprocessing (SMP) - Correct Option: (d) Symmetric Multiprocessing (SMP)
- Explanation: In SMP systems, all processors share a single, common memory, and each processor has equal access to the memory.
Q(46) Which are the two signals in the DMA controller used by the CPU to facilitate?
- Options:
(a) Input-output
(b) Bus and control
(c) Bus grant and Bus request
(d) Bus grant and Bus revoke - Correct Option: (c) Bus grant and Bus request
- Explanation: In Direct Memory Access (DMA), the CPU uses "bus request" and "bus grant" signals to control access to the system bus. The CPU requests the bus, and the DMA controller grants it.
Q(47) In the Vectored interrupt mechanism, the interrupting device provides the address of the interrupt service routine using which of the following?
- Options:
(a) Data bus
(b) Interrupt service
(c) Control signal
(d) Address bus - Correct Option: (d) Address bus
- Explanation: In the vectored interrupt mechanism, the interrupting device provides the address of the interrupt service routine (ISR) to the processor via the address bus.
Q(48) In which of the following mechanisms is the address of the interrupt service routine provided by the interrupting device?
- Options:
(a) Hardware interrupt
(b) Software interrupt
(c) Priority interrupt
(d) Vectored interrupt - Correct Option: (d) Vectored interrupt
- Explanation: In a vectored interrupt, the interrupting device provides the address of the ISR, unlike hardware or software interrupts, which do not directly provide the ISR's address.
Q(49) Identify the incorrect statement with respect to auxiliary memory.
- Options:
(a) It has large capacity
(b) It is inexpensive in cost
(c) It can be used in RAM construction
(d) It often serves as an option for backup services - Correct Option: (c) It can be used in RAM construction
- Explanation: Auxiliary memory, such as hard drives or optical disks, is not used in RAM construction. It is often used for backup services and has a larger capacity than RAM but is slower.
Q(50) The interrupt enable flip-flop IEN can be set or cleared by which of the following?
- Options:
(a) Program instructions
(b) Interrupt service
(c) ALU
(d) DMA - Correct Option: (a) Program instructions
- Explanation: The interrupt enable flip-flop (IEN) is set or cleared by program instructions, which control whether interrupts are enabled or disabled.
Q(51) How many 2⁴ decoders are needed in order to make a 4⁴ 16-line decoder?
- Options:
(a) 4
(b) 5
(c) 8
(d) 3 - Correct Option: (a) 4
- Explanation: To build a 4x16 decoder, four 2x4 decoders are used, each decoding a portion of the address space.
Q(52) What is the number of data inputs in a 4x1 Multiplexer?
- Options:
(a) 0 to 3
(b) 0 to 4
(c) 1 to 8
(d) 0 to 7 - Correct Option: (b) 0 to 4
- Explanation: A 4x1 multiplexer has four data inputs (0 to 3), one output, and two control inputs to select between the data inputs.
Q(53) Register R has value 11011101. Determine the sequence after logical shift left.
- Options:
(a) 1011110
(b) 11011101
(c) 01101110
(d) 10000100 - Correct Option: (c) 01101110
- Explanation: A logical shift left moves all bits to the left and inserts a 0 at the rightmost bit. For 11011101, the result after the shift will be 01101110.
Q(54) Register R has value 10111010. Determine the sequence after a Circular shift right.
- Options:
(a) 01011100
(b) 00101110
(c) 01101110
(d) 11011101 - Correct Option: (d) 11011101
- Explanation: In a circular shift right, the rightmost bit is shifted to the leftmost position. For 10111010, the result is 11011101.
Q(55) A common bus system has 16 registers of 32 bits each. How many multiplexers are there in the bus?
- Options:
(a) 16
(b) 32
(c) 20
(d) 12 - Correct Option: (b) 32
- Explanation: To connect 16 registers to the bus, there would need to be 32 multiplexers (one for each bit of the 32-bit registers).
Q(56) A shift register is defined as:
- Options:
(a) The register capable of shifting information to another register
(b) The register capable of shifting information either to the right or to the left
(c) The register capable of shifting information to the right only
(d) The register capable of shifting information to the left only - Correct Option: (b) The register capable of shifting information either to the right or to the left
- Explanation: A shift register is capable of shifting information in both directions: to the right or to the left.
Q(57) What is the relationship between Input Output processor and Direct memory access?
- Options:
(a) Many computers combine the interface logic with the requirements for direct memory access into one unit and call it an I/O processor
(b) Many computers are used to implement the logic of Direct memory access without using I/O processor
(c) Transfer of data under programmed I/O is between CPU and Memory
(d) Transfer of data under programmed I/O is between CPU and ALU - Correct Option: (a) Many computers combine the interface logic with the requirements for direct memory access into one unit and call it an I/O processor
- Explanation: Many systems combine the DMA controller and I/O interface logic into a single unit called the I/O processor, which handles both I/O operations and DMA.
Q(58) If while running an instruction the following information is supplied, opcode = 111, I = 0, what will be the type of instruction?
- Options:
(a) Memory reference instructions
(b) Register reference instructions
(c) Input-Output instructions
(d) Interrupt instructions - Correct Option: (a) Memory reference instructions
- Explanation: The opcode "111" and I = 0 typically indicate a memory reference instruction, as the I flag often indicates the use of memory.
Q(59) Which statement is true for priority interrupt in a system?
- Options:
(a) It is a system that establishes a priority over the various sources to determine which condition is to be serviced first
(b) It is a system that establishes a priority over the various sources to determine which condition is to be serviced second and later
(c) It is a system that establishes a priority over the various sources to determine which condition is to be serviced last
(d) All options are correct - Correct Option: (a) It is a system that establishes a priority over the various sources to determine which condition is to be serviced first
- Explanation: A priority interrupt system decides which interrupt source should be serviced first based on a predefined priority.
Q(60) Which statement is true for Daisy chaining priority interrupt in a system?
- Options:
(a) The device with the highest priority is placed in the last position, followed by lower-priority devices
(b) The device with the highest priority is placed in the first position, followed by lower-priority devices
(c) The device with the lowest priority is placed in the rank position, followed by lower-priority devices
(d) It does prioritize the devices according to the rank order - Correct Option: (b) The device with the highest priority is placed in the first position, followed by lower-priority devices
- Explanation: In Daisy chaining, the device with the highest priority is at the front, and lower-priority devices are chained after it.