Q1. What is the number of inputs and outputs of a half-adder?
Options:
a. 2 inputs and 1 output
b. 2 inputs and 2 outputs
c. 2 inputs and 3 outputs
d. 3 inputs and 2 outputs
Correct Option: b. 2 inputs and 2 outputs
Explanation: A half-adder computes the sum and carry of two binary inputs, producing two outputs: Sum and Carry.
Q2. A register is a combination of
Options:
a. Flip-flops
b. Logic gates
c. Both a and b
d. None of the above
Correct Option: c. Both a and b
Explanation: A register is made up of flip-flops for storage and logic gates for control operations.
Q3. Which one of the following multiplexers would have a 4-bit data select input?
Options:
a. 4:1 multiplexer
b. 2:1 multiplexer
c. 16:1 multiplexer
d. 8:1 multiplexer
Correct Option: c. 16:1 multiplexer
Explanation: A 4-bit data select input can address inputs, corresponding to a 16:1 multiplexer.
Q4. In which of the following addressing modes, the operand value is directly specified?
Options:
a. Immediate
b. Direct
c. Register Direct
d. Relative
Correct Option: a. Immediate
Explanation: In immediate addressing mode, the operand is provided directly in the instruction.
Q5. Primary condition to input data into a register
Options:
a. Clk = 1 & Load = 1
b. Clk = 0 & Load = 0
c. Clk = 0 & Load = 1
d. Clk = 1 & Load = 0
Correct Option: a. Clk = 1 & Load = 1
Explanation: Data can only be loaded into the register when both the clock signal and the load signal are active (1).
Q6. The two-input MUX would have
Options:
a. 1 select line
b. 2 select lines
c. 4 select lines
d. 3 select lines
Correct Option: a. 1 select line
Explanation: A two-input multiplexer requires one select line to choose between the two inputs.
Q7. Number of multiplexers is equivalent to the number of _______ in the bus system
Options:
a. Registers
b. Bits
c. Size
d. Connections
Correct Option: b. Bits
Explanation: The number of multiplexers corresponds to the number of bits in the data path.
Q8. A tri-state buffer has
Options:
a. High-impedance state
b. Control method
c. Controlled output
d. None
Correct Option: a. High-impedance state
Explanation: A tri-state buffer has three states: 1, 0, and a high-impedance (Z) state to disconnect the output.
Q9. Which one of the following addressing modes adds the content of the program counter to the address part of the instruction to obtain the effective address?
Options:
a. Absolute Addressing
b. Register Addressing
c. Register Indirect Addressing
d. Indexed Addressing
Correct Option: d. Indexed Addressing
Explanation: Indexed addressing uses the program counter content and the address part of the instruction to calculate the effective address.
Q10. In order to realize an adder that can add two 16-bit numbers, how many full adders and half adders would be required?
Options:
a. 10 half adders and 17 full adders
b. 1 half adder and 15 full adders
c. 15 half adders and 1 full adder
d. 17 half adders and 0 full adders
Correct Option: b. 1 half adder and 15 full adders
Explanation: The first bit uses a half adder (no carry-in), and the remaining 15 bits require full adders to account for carry.
Q11. Registers capable of shifting in one direction are
Options:
a. Universal shift register
b. Unidirectional shift register
c. Unipolar shift register
d. Unique shift register
Correct Option: b. Unidirectional shift register
Explanation: A unidirectional shift register allows data to be shifted in only one direction (either left or right).
Q12. RTL stands for
Options:
a. Random transfer language
b. Register transfer language
c. Arithmetic transfer language
d. All of these
Correct Option: b. Register transfer language
Explanation: RTL represents data transfers and operations in terms of registers and the data paths between them.
Q13. Overflow condition occurs in which of the following logic shift micro-operations?
Options:
a. Arithmetic shift right
b. Arithmetic shift left
c. Logical shift left
d. Circular left shift
Correct Option: b. Arithmetic shift left
Explanation: Overflow occurs in arithmetic shift left when the result exceeds the capacity of the destination register.
Q14. Which of the following are known as universal gates?
Options:
a. NAND & NOR
b. AND & OR
c. XOR & OR
d. None of the mentioned
Correct Option: a. NAND & NOR
Explanation: NAND and NOR gates are universal because any digital circuit can be implemented using only these gates.
Q15. Pipe-lining is a unique feature of
Options:
a. RISC
b. CISC
c. ISA
d. IANA
Correct Option: a. RISC
Explanation: RISC architectures are designed to support pipelining for faster and more efficient instruction execution.
Q16. In which type of addressing mode does the instruction specify the register in the CPU whose contents give the address of the operand in memory?
Options:
a) Auto increment mode
b) Register indirect mode
c) Immediate
d) Indirect mode
Correct Option: b) Register indirect mode
Explanation: In register indirect mode, the instruction specifies a register that holds the memory address of the operand.
Q17. In which address mode are the operands specified implicitly in the definition of the instruction?
Options:
a) Implied mode
b) Immediate mode
c) Register mode
d) Direct address mode
Correct Option: a) Implied mode
Explanation: In implied mode, the operand is not explicitly mentioned; it is implied by the instruction itself.
Q18. In which addressing mode does the instruction specify the memory address used as the effective address to access the operand?
Options:
a) Implied mode
b) Immediate mode
c) Direct address mode
d) Indirect address mode
Correct Option: c) Direct address mode
Explanation: In direct address mode, the memory address of the operand is explicitly specified in the instruction.
Q19. Which address instruction format results in the shortest programs when evaluating arithmetic expressions?
Options:
a) One address instruction
b) Two address instruction
c) Zero address instruction
d) Three address instruction
Correct Option: c) Zero address instruction
Explanation: Zero-address instructions use a stack for computation, requiring fewer instructions to evaluate expressions.
Q20. When an instruction is required to be brought from memory to the CPU, which one of the following buses is fetched?
Options:
a) Address bus
b) Data bus
c) Control bus
d) Peripheral bus
Correct Option: b) Data bus
Explanation: The data bus is used to transfer data between memory and the CPU.
Q21. Which of the following is not a data transfer instruction?
Options:
a) Load
b) Clear
c) Store
d) Move
Correct Option: b) Clear
Explanation: "Clear" is not a data transfer instruction; it is a data manipulation instruction used to set a value to zero.
Q22. Which of the following pairs of instructions is typical for arithmetic operations?
Options:
a) Clear and Complement
b) Increment and Decrement
c) Arithmetic shift right and Add
d) Subtract and Exclusive-OR
Correct Option: b) Increment and Decrement
Explanation: Arithmetic instructions typically involve mathematical operations like addition, subtraction,Increment and Decrement.
Q23. The control unit of a computer system is designed to go through which of the following instruction cycles?
Options:
a) Fetch
b) Decode
c) Execute
d) All of the above
Correct Option: d) All of the above
Explanation: The instruction cycle includes fetching the instruction, decoding it, and executing it.
Q24. Which of the following statements is correct about RISC architecture?
Options:
a) Makes use of microprogrammed control unit
b) Has smaller cache as compared to CISC processors
c) Supports many addressing modes
d) Makes use of hardwired control unit
Correct Option: d) Makes use of hardwired control unit
Explanation: RISC architectures use hardwired control units for faster instruction execution.
Q25. In the zero-address instruction method, the operands are stored in ______.
Options:
a) Registers
b) Accumulators
c) Push-down stack
d) Cache
Correct Option: c) Push-down stack
Explanation: Zero-address instructions use a stack to hold operands and results.
Q26. The top of the stack can be denoted by ______.
Options:
a) Program counter (PC)
b) Address register (AR)
c) Stack pointer (SP)
d) Instruction register (IR)
Correct Option: c) Stack pointer (SP)
Explanation: The stack pointer (SP) points to the top of the stack in memory.
Q27. Which mode specifies the instruction itself?
Options:
a) Implied mode
b) Immediate mode
c) Register mode
d) Register Indirect mode
Correct Option: b) Immediate mode
Explanation: In immediate mode, the operand is provided directly in the instruction itself.
Q28. A basic instruction that can be interpreted by a computer generally has ______.
Options:
a) An operand and an address
b) A decoder and an accumulator
c) A sequence register and decoder
d) An address and decoder
Correct Option: a) An operand and an address
Explanation: Instructions typically include an operation to perform (operand) and the address of the data.
Q29. Which of the following is responsible for coordinating various operations using timing signals?
Options:
a) ALU
b) Control unit
c) Memory unit
d) I/O unit
Correct Option: b) Control unit
Explanation: The control unit generates timing and control signals to synchronize all operations.
Q30. Which of the following is used as storage locations in both the ALU and the control section of a computer?
Options:
a) Accumulator
b) Register
c) Adder
d) Decoder
Correct Option: b) Register
Explanation: Registers are used for temporary storage in both the ALU and the control section.
Q31. The function of program counter (PC) holds
Options:
(a) Temporary
(b) Address for memory
(c) Memory operand
(d) Address for instruction
Correct Option: d) Address for instruction
Explanation: The program counter (PC) holds the address of the next instruction to be executed in the program.
Q32. The Program Counter (PC)
Options:
(a) Is a register
(b) During execution of the current instruction, its content changes
(c) Both (a) and (b)
(d) None of these
Correct Option: c) Both (a) and (b)
Explanation: The PC is a special register that updates its value to point to the next instruction after each execution.
Q33. The register used as a working area in the CPU is
Options:
(a) Program counter
(b) Instruction register
(c) Instruction decoder
(d) Accumulator
Correct Option: d) Accumulator
Explanation: The accumulator is a general-purpose register used for arithmetic and logical operations.
Q34. Which of the following registers is used in the control unit of the CPU to indicate the next instruction to be executed?
Options:
(a) Accumulator
(b) Index register
(c) Instruction decoder
(d) Program counter
Correct Option: d) Program counter
Explanation: The program counter keeps track of the address of the next instruction to execute.
Q35. The register that contains the data to be written into or read out of the addressed location is called
Options:
(a) Memory address register
(b) Memory data register
(c) Program counter
(d) Index register
Correct Option: b) Memory data register
Explanation: The memory data register (MDR) holds data to be transferred to or from memory.
Q36. The sequence of events that happen during a typical fetch operation is
Options:
(a) PC → Memory → IR
(b) PC → Memory → MDR → IR
(c) PC → MAR → Memory → MDR → IR
(d) PC → MAR → Memory → IR
Correct Option: c) PC → MAR → Memory → MDR → IR
Explanation: During the fetch cycle, the PC contents are copied to the MAR, the data is fetched from memory to MDR, and finally, the instruction is loaded into the IR.
Q37. If internal data forwarding is used to speed up the performance of a CPU, the sequence of operations can be replaced by
Given Operations:
R1 ← M[100]
R2 ← R1
R3 ← R2
Options:
(a) R1 ← R3
(b) R2 ← M[100]; R1 ← R2; R3 ← R2
(c) R1 ← M[100]; R2 ← R3; R3 ← R2
(d) R1 ← R2; R2 ← R3; R1 ← M[100]
Correct Option: b) R2 ← M[100]; R1 ← R2; R3 ← R2
Explanation: Internal data forwarding allows bypassing registers and directly assigning memory to subsequent operations.
Q38. Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
Explanation: The memory references are calculated based on the program's instructions and the number of iterations.
Correct Option: d) 110
Explanation: The program iteratively updates memory starting from 2000. The content at location 2010 will increase by 10 due to the loop.
Q40. Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
Instruction Operation Instruction size (no. of words)
MOV R1, (3000) R1 ← M[3000] 2
LOOP:
MOV R2, M[R3] R2 ← M[R3] 1
ADD R2, R1 R2 ← R1 + R2 1
MOV (R3), R2 R2 M[R3] ← R2 1
INC R3 R3 ← R3 + 1 1
DEC R1 R1 ← R1 - 1 1
BNZ LOOP Branch on not zero 1
HALT Stop 2
Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimals.
Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?
Correct Option: c) 1024
Explanation: Since the instruction size is word-based (4 bytes per word), the address increments accordingly. The "INC R3" instruction starts at 1020 and completes at 1024. If interrupted, the next instruction's address (1024) is saved.