- (a) Direct mode
- (b) Register mode
- (c) Based mode
- (d) Indexed mode
Correct Option: (c) Based mode
Explanation: In base addressing mode, the offset is obtained by adding the displacement value to the contents of a base register.
2. The following code is used in _________________ comparator:
If X > Y then G <= 1; else if X < Y then L <= 1; else E <= 1;
- (a) ALU
- (b) Arithmetic
- (c) Logic
- (d) None
Correct Option: (c) Logic
Explanation: This is a comparison operation that checks conditions like "greater than," "less than," and "equal to," typically used in a logic comparator.
3. Every 1-bit Comparator has ____________ number of gates.
- (a) 1
- (b) 2
- (c) 3
- (d) 4
Correct Option: (c) 3
Explanation: A 1-bit comparator requires at least three gates: one XOR gate for difference, one AND gate for checking "greater than," and one OR gate for "equal to" logic.
4. ST is categorized as __________ instruction.
- (a) Data transfer
- (b) Control
- (c) String
- (d) None
Correct Option: (a) Data transfer
Explanation: ST (store) is typically categorized as a data transfer instruction because it moves data from a register to memory.
5. Delay in N Bit Comparator is given by:
- (a) (1·n + 1) ·t
- (b) (2n + 1) ·t
- (c) (3·n + 1) ·t
- (d) (4·n + 1) ·t
Correct Option: (b) (2n + 1) ·t
Explanation: The delay in an N-bit comparator depends on the number of bits and gates used in comparison; it is proportional to 2n + 1 gates.
6. How many AND, OR, and EXOR gates are required for the configuration of a full adder?
- (a) 1, 2, 2
- (b) 2, 1, 2
- (c) 3, 1, 2
- (d) 4, 0, 1
Correct Option: (b) 2, 1, 2
Explanation: A full adder requires 2 AND gates, 1 OR gate, and 2 XOR gates to perform the sum and carry operations.
7. The addressing mode which makes use of in-direction pointers is ______.
- (a) Indirect addressing mode
- (b) Index addressing mode
- (c) Relative addressing mode
- (d) Offset addressing mode
Correct Option: (a) Indirect addressing mode
Explanation: In indirect addressing mode, the address of the operand is stored in memory or a register, which acts as a pointer to the actual operand.
8. With reference to process in VHDL, pick the correct one:
- Contains sequential sentences to define its own behavior
- Communicates with other processes and concurrent sentences by means of signals
- Each process is sensitive to events on specific signals or conditions to launch again its execution
- The sensitivity list identifies the signals to which this process is sensitive (“stop/wait” condition).
- (A) 1, 2, 3
- (B) 2, 3, 4
- (C) 3, 4, 1
- (D) 1, 2, 3, 4
Correct Option: (D) 1, 2, 3, 4
Explanation: All the points listed are accurate about processes in VHDL, as processes contain sequential behavior, communicate via signals, and have sensitivity lists.
9. If the top 2 elements of a stack are kept in a register, then each pop operation in stack organization takes _______ memory references.
- (a) 0
- (b) 1
- (c) 2
- (d) 3
Correct Option: (b) 1
Explanation: If the top 2 elements are already in registers, then popping only requires one memory reference to remove the top element.
10. In which of these modes, the immediate operand is included in the instruction itself?
- (a) Register operand mode
- (b) Immediate operand mode
- (c) Register and immediate operand mode
- (d) None of the mentioned
Correct Option: (b) Immediate operand mode
Explanation: In immediate operand mode, the operand is embedded directly within the instruction itself.
11. Add #45, when this instruction is executed the following happens _______
- (a) The processor raises an error and requests for one more operand
- (b) The value stored in memory location 45 is retrieved and one more operand is requested
- (c) The value 45 gets added to the value on the stack and is pushed onto the stack
- (d) None of the mentioned
Correct Option: (c) The value 45 gets added to the value on the stack and is pushed onto the stack
Explanation: The instruction adds the value 45 to the stack, typically for stack-based operations like pushing an operand.
12. With reference to VHDL, which one is correct:
- The VHDL is a strongly typed language
- A data type defines a set of fixed and static values
- Any language object belongs to a specific data type
- (A) 1, 2
- (B) 2, 3
- (C) 3, 1
- (D) All
Correct Option: (D) All
Explanation: VHDL is a strongly typed language, data types are fixed and static, and every object belongs to a specific type.
13. In the following indexed addressing mode instruction, MOV 5(R1), the location of the effective address is ______.
- (a) EA = 5 + R1
- (b) EA = R1
- (c) EA = [R1]
- (d) EA = 5 + [R1]
Correct Option: (a) EA = 5 + R1
Explanation: In indexed addressing mode, the effective address (EA) is computed by adding the offset (5) to the content of register R1.
14. Choose the correct one:
S1. Immediate addressing mode gives the operand immediate to the processor.
S2. Immediate addressing mode is used to handle the constant increments.
(a) S1, S2
(b) S1
(c) S2
(d) None
Correct Option: (a) S1, S2
Explanation: Both statements are correct. Immediate addressing provides the operand directly in the instruction and is often used for constants.
15. Pick the correct one from the following:
S1: In register addressing mode, the operand is present in the register itself.
S2: In register addressing mode, the address of the operand is present in the register itself.
(a) S1
(b) S2
(c) Both
(d) None
Correct Option: (a) S1
Explanation: In register addressing mode, the operand is stored directly in the register, not the address of the operand.
16. In the IBM 360 General Purpose register machine, the number of registers is:
- (a) 10
- (b) 12
- (c) 14
- (d) 16
Correct Option: (b) 12
Explanation: The IBM 360 General Purpose register machine has 12 registers in total.
17. BEQZ instruction is _______ instruction.
- (a) ALU
- (b) Data Transfer
- (c) Control
- (d) None
Correct Option: (c) Control
Explanation: BEQZ (Branch if Equal to Zero) is a control instruction, as it alters the program flow based on a condition.
18. If the top 2 elements of a stack are kept in registers, then each push operation in stack organization takes _______ memory references.
- (a) 1
- (b) 2
- (c) 3
- (d) 4
Correct Option: (b) 2
Explanation: A push operation would require two memory references: one to store the value in the register and one to update the stack pointer.
19. For binary adder, carry in is given by ________ equation:
Answer: The carry in for a binary adder is typically given by the equation .
20. In register Indirect mode, the number of memory references is _________.
Answer: 2 memory references. In register indirect addressing, the register contains the address of the operand, and a memory access is required to fetch the data from that address.
12. Number of memory references in immediate addressing mode is _________.
Answer: 1 memory reference. In immediate addressing mode, the operand is directly included in the instruction itself, so no additional memory references are needed.
21. The microprocessor of a computer can operate on any information if it is present in ______________ only.
- (a) Program Counter
- (b) Flag
- (c) Main Memory
- (d) Secondary Memory
Correct Option: (c) Main Memory
Explanation: The microprocessor can only operate on data that is stored in main memory or registers, not directly on secondary memory.
22. Which of the following addressing methods does the instruction, MOV AX,[BX] represent?
- (a) Register indirect addressing mode
- (b) Direct addressing mode
- (c) Register addressing mode
- (d) Register relative addressing mode
Correct Option: (a) Register indirect addressing mode
Explanation: The instruction MOV AX, [BX] uses the contents of the register BX as the memory address from which the data is moved to the AX register, making it register indirect addressing.
23. Half-adders have a major limitation in that they cannot __________.
- (a) Accept a carry bit from a present stage
- (b) Accept a carry bit from the next stage
- (c) Accept a carry bit from a previous stage
- (d) Accept a carry bit from the following stages
Correct Option: (c) Accept a carry bit from a previous stage
Explanation: A half-adder cannot accept a carry input from the previous stage; it only adds the two inputs and generates a carry output.
24. Let A and B be the inputs of a Subtractor; then the borrow will be ___________
- (a) A AND B’
- (b) A’ AND B
- (c) A OR B
- (d) A AND B
Correct Option: (a) A AND B’
Explanation: The borrow in a subtractor is generated when A is 0 and B is 1, which is represented by .
25. The subtractor has two outputs, BORROW and DIFFERENCE. Since the difference output of a subtractor is given by , and this is the output of an XOR gate. So, the final difference output is . (True ___ False ___ )
Correct Option: True
Explanation: The difference in binary subtraction is indeed given by , which is the result of an XOR operation.
26. The enable input is also known as ___________
- (a) Select input
- (b) Decoded input
- (c) Strobe
- (d) Sink
Correct Option: (c) Strobe
Explanation: The enable input in logic circuits is sometimes referred to as a strobe, as it controls when the data should be latched or transmitted.
27. A 2^n:1 MUX can implement all logic functions of _________ variables without any additional circuitry.
Answer: A 2^n:1 MUX can implement all logic functions of n variables.
28. Without any additional circuitry, an 8:1 MUX can be used to obtain ____________
- (a) Some but not all Boolean functions of 3 variables
- (b) All functions of 3 variables but none of 4 variables
- (c) All functions of 3 variables and some but not all of 4 variables
- (d) All functions of 4 variables
Correct Option: (b) All functions of 3 variables but none of 4 variables
Explanation: An 8:1 MUX can implement any Boolean function of 3 variables, but not all functions of 4 variables because it would require more than 8 input lines to cover all combinations of 4 variables.
29. In the design of an ALU, which of the following logic gates are primarily used for arithmetic operations like addition and subtraction?
- (a) AND
- (b) OR
- (c) XOR
- (d) NAND
Correct Option: (c) XOR
Explanation: The XOR gate is primarily used in arithmetic operations like addition and subtraction for calculating the sum or difference. It is used to perform the "add without carry" operation.
30. Which of the following is true about RISC processors?
- (a) RISC processors have a large number of complex instructions
- (b) RISC processors have a smaller instruction set and most instructions are executed in one cycle
- (c) RISC processors require multiple cycles to execute each instruction
- (d) RISC processors use variable-length instructions
Correct Option: (b) RISC processors have a smaller instruction set and most instructions are executed in one cycle
Explanation: RISC processors have a simplified instruction set that allows most instructions to execute in a single clock cycle.
31. What is the maximum possible number of instructions that can be executed in a single clock cycle in a superscalar processor?
- (a) 1
- (b) 2
- (c) 3
- (d) More than 3
Correct Option: (d) More than 3
Explanation: In superscalar processors, multiple instructions can be executed in parallel in a single clock cycle, so the maximum number can be more than 3, depending on the number of execution units available.
32. Which of the following is true about memory-mapped I/O?
- (a) Memory-mapped I/O uses a separate address space for I/O devices
- (b) In memory-mapped I/O, I/O devices are accessed through specific instructions
- (c) Memory-mapped I/O treats I/O devices as part of the regular memory address space
- (d) Memory-mapped I/O is used only for input devices
Correct Option: (c) Memory-mapped I/O treats I/O devices as part of the regular memory address space
Explanation: In memory-mapped I/O, input/output devices are mapped to specific memory addresses, and the processor accesses them using standard memory instructions.
33. Which of the following addressing modes is used in the instruction "MOV AX, [BX]"?
- (a) Register addressing
- (b) Direct addressing
- (c) Indirect addressing
- (d) Immediate addressing
Correct Option: (c) Indirect addressing
Explanation: The instruction MOV AX, [BX] uses the value in the BX register as a pointer to memory, so it is using indirect addressing.
34. Which of the following microprocessor architectures allows for more complex instructions to be executed in a single cycle?
- (a) CISC
- (b) RISC
- (c) EPIC
- (d) None of the above
Correct Option: (a) CISC
Explanation: CISC (Complex Instruction Set Computer) architectures allow more complex instructions to be executed in a single cycle, which contrasts with RISC (Reduced Instruction Set Computer) that uses simpler instructions.
35. What is the function of the Program Counter (PC) in a microprocessor?
- (a) It stores the current instruction being executed
- (b) It stores the address of the next instruction to be executed
- (c) It stores the result of the last executed instruction
- (d) It stores data values
Correct Option: (b) It stores the address of the next instruction to be executed
Explanation: The Program Counter holds the memory address of the next instruction that is to be fetched and executed.
36. What is the primary advantage of using a stack in a computer system?
- (a) It allows for random access to memory
- (b) It supports the use of recursive functions
- (c) It provides faster data access
- (d) It enables efficient memory allocation
Correct Option: (b) It supports the use of recursive functions
Explanation: The stack is useful for supporting recursive functions because it allows for pushing and popping function calls and return addresses in a Last In, First Out (LIFO) order.
37. In a pipeline, what is the main cause of a stall?
- (a) Data hazard
- (b) Control hazard
- (c) Structural hazard
- (d) All of the above
Correct Option: (d) All of the above
Explanation: Stalls in a pipeline can be caused by data hazards, control hazards (e.g., branches), and structural hazards (e.g., insufficient resources for executing an instruction).
38. Which of the following is a typical example of a control unit in a microprocessor?
- (a) ALU
- (b) Register File
- (c) Decoder
- (d) Program Counter
Correct Option: (c) Decoder
Explanation: The decoder in the control unit is responsible for interpreting the instruction and generating the corresponding control signals that direct the operation of other parts of the processor.